Intel Pentium CPU Instruction Set Reference
DIV instruction - Unsigned Divide
| Code |
Mnemonic |
Description |
| F6 /6 |
DIV r/m8 |
Unsigned divide AX by r/m8; AL = Quotient, AH = Remainder |
| F7 /6 |
DIV r/m16 |
Unsigned divide DX:AX by r/m16; AX = Quotient, DX = Remainder |
| F7 /6 |
DIV r/m32 |
Unsigned divide EDX:EAX by r/m32 doubleword; EAX = Quotient, EDX = Remainder |
Description
Divides (unsigned) the value in the AX register, DX:AX register pair, or EDX:EAX register pair (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a memory location. The action of this instruction depends on the operand size, as shown in the following table:
| Operand Size |
Dividend |
Divisor |
Quotient |
Remainder |
Maximum Quotient |
| Word / Byte |
AX |
r/m8 |
AL |
AH |
255 |
| Doubleword / Word |
DX:AX |
r/m16 |
AX |
DX |
65,535 |
| Quadword / Doubleword |
EDX:EAX |
r/m32 |
EAX |
EDX |
4,294,967,295 (2^32 - 1) |
Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.
| Operands |
Bytes |
Clocks |
| r8 |
2 |
17 |
NP |
| r16 |
2 |
25 |
NP |
| r32 |
2 |
41 |
NP |
| mem8 |
2 + d(0 - 2) |
17 |
NP |
| mem16 |
2 + d(0 - 2) |
25 |
NP |
| mem32 |
2 + d(0 - 2) |
41 |
NP |
Note:
| implied dividend |
|
operand |
|
quotient |
remainder |
| AX |
/ |
byte |
= |
AL |
AH |
| DX:AX |
/ |
word |
= |
AX |
DX |
| EDX:EAX |
/ |
dword |
= |
EAX |
EDX |
Flags
| ID |
unaffected |
DF |
unaffected |
| VIP |
unaffected |
IF |
unaffected |
| VIF |
unaffected |
TF |
unaffected |
| AC |
unaffected |
SF |
undefined |
| VM |
unaffected |
ZF |
undefined |
| RF |
unaffected |
AF |
undefined |
| NT |
unaffected |
PF |
undefined |
| IOPL |
unaffected |
CF |
undefined |
| OF |
undefined |
