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Intel Pentium CPU Instruction Set Reference

ADD instruction - Add

Code Mnemonic Description
04 ib ADD AL, imm8 Add imm8 to AL
05 iw ADD AX, imm16 Add imm16 to AX
05 id ADD EAX, imm32 Add imm32 to EAX
80 /0 ib ADD r/m8, imm8 Add imm8 to r/m8
81 /0 iw ADD r/m16, imm16 Add imm16 to r/m16
81 /0 id ADD r/m32, imm32 Add imm32 to r/m32
83 /0 ib ADD r/m16, imm8 Add sign-extended imm8 to r/m16
83 /0 ib ADD r/m32, imm8 Add sign-extended imm8 to r/m32
00 / r ADD r/m8, r8 Add r8 to r/m8
01 / r ADD r/m16, r16 Add r16 to r/m16
01 / r ADD r/m32, r32 Add r32 to r/m32
02 / r ADD r8, r/m8 Add r/m8 to r8
03 / r ADD r16, r/m16 Add r/m16 to r16
03 / r ADD r32, r/m32 Add r/m32 to r32


Adds the first operand (destination operand) and the second operand (source operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The ADD instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.

Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2 + d(0, 2) 3 UV
reg, mem 2 + d(0, 2) 2 UV
reg, imm 2 + i(1, 2) 1 UV
mem, imm 2 + d(0, 2) + i(1, 2) 3 UV ( not pairable if there is a displacement and immediate)
acc, imm 1 + i(1, 2) 1 UV


ID unaffected DF unaffected
VIP unaffected IF unaffected
VIF unaffected TF unaffected
AC unaffected SF sets according to the result.
VM unaffected ZF sets according to the result.
RF unaffected AF sets according to the result.
NT unaffected PF sets according to the result.
IOPL unaffected CF sets according to the result.
OF sets according to the result.