| rel8 | A relative address in the range from 128 bytes before the end of the instruction to 127 bytes after the end of the instruction. |
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| rel16, rel32 | A relative address within the same code segment as the instruction assembled. The rel16 symbol applies to instructions with an operand-size attribute of 16 bits; the rel32 symbol applies to instruction switch an operand-size attribute of 32 bits. |
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| ptr16:16, ptr16:32 | A far pointer, typically in a code segment different from that of the instruction. The notation 16:16indicates that the value of the pointer has two parts. The value to the left of the colon is a 16-bit selector or value destined for the code segment register. The value to the right corresponds to the offset within the destination segment. The ptr16:16 symbol is used when the instruction's operand-size attribute is 16bits; the ptr16:32 symbol is used when the operand-size attribute is 32 bits. |
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| r8 | One of the byte general-purpose registers AL, CL, DL, BL, AH, CH, DH, or BH. |
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| r16 | One of the word general-purpose registers AX, CX, DX, BX, SP, BP, SI, or DI. |
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| r32 | One of the double word general-purpose registers EAX, ECX, EDX, EBX, ESP, EBP, ESI, or EDI. |
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| imm8 | An immediate byte value. The imm8 symbol is assigned number between –128 and +127 inclusive. For instructions in which imm8 is combined with a word or doubleword operand, the immediate value is sign-extended to form a word or doubleword. The upper byte of the word is filled with the topmost bit of the immediate value. |
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| imm16 | An immediate word value used for instructions whose operand-size attribute is 16 bits. This is a number between –32,768 and +32,767 inclusive. |
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| imm32 | An immediate doubleword value used for instructions whose operand-size attribute is 32 bits. It allows the use of a number between +2,147,483,647 and–2,147,483,648 inclusive. |
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| r/m8 | A byte operand that is either the contents of a byte general-purpose register (AL, BL, CL, DL, AH, BH, CH, and DH), or a byte from memory. |
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| r/m16 | A word general-purpose register or memory operand used for instructions whose operand-size attribute is16 bits. The word general-purpose registers are: AX, BX, CX, DX, SP, BP, SI, and DI. The contents of memory are found at the address provided by the effective address computation. |
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| r/m32 | A doubleword general-purpose register or memory operand used for instructions whose operand-size attribute is 32 bits. The doubleword general-purpose registers are: EAX, EBX, ECX, EDX, ESP, EBP, ESI, and EDI. The contents of memory are found at the address provided by the effective address computation. |
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| m | A 16- or 32-bit operand in memory. |
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| m8 | A byte operand in memory, usually expressed as a variable or array name, but pointed to by the DS:(E)SI or ES:(E)DI registers. This nomenclature is used only with the string instructions and the XLAT instruction. |
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| m16 | A word operand in memory, usually expressed as a variable or array name, but pointed to by the DS:(E)SI or ES:(E)DI registers. This nomenclature is used only with the string instructions. |
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| m32 | A doubleword operand in memory, usually expressed as a variable or array name, but pointed to by the DS:(E)SI or ES:(E)DI registers. This nomenclature is used only with the string instructions. |
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| m64 | A memory quadword operand in memory. This nomenclature is used only with the CMPXCHG8Binstruction. |
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| m16:16, m16:32 | A memory operand containing a far pointer composed of two numbers. The number to the left of the colon corresponds to the pointer's segment selector. The number to the right corresponds to its offset. |
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| m16&32, m16&16, m32&32 | A memory operand consisting of data item pairs whose sizes are indicated on the left and the right side of the ampersand. All memory addressing modes are allowed. The m16&16 and m32&32 operands are used by the BOUND instruction to provide an operand containing an upper and lower bounds for array indices. The m16&32operand is used by LIDT and LGDT to provide a word with which to load the limit field, and a doubleword with which to load the base field of the corresponding GDTR and IDTR registers. |
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| moffs8, moffs16, moffs32 | A simple memory variable (memory offset) of type byte, word, or doubleword used by some variants of the MOV instruction. The actual address is given by a simple offset relative to the segment base. No ModR/M byte is used in the instruction. The number shown with moffs indicates its size, which is determined by the address-size attribute of the instruction. |
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| Sreg | A segment register. The segment register bit assignments are ES=0, CS=1, SS=2, DS=3, FS=4, and GS=5. |
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| m32real, m64real, m80real | A single-, double-, and extended-real (respectively) floating-point operand in memory. |
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| m16int, m32int, m64int | A word-, short-, and long-integer (respectively) floating-point operand in memory. |
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| ST or ST(0) | The top element of the FPU register stack. |
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| ST(i) | The i th element from the top of the FPU register stack. (i = 0 through 7) |
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| mm | An MMX™ register. The 64-bit MMX registers are: MM0 through MM7. |
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| mm/m32 | The low order 32 bits of an MMX register or a 32-bit memory operand. The 64-bit MMX registers are: MM0through MM7. The contents of memory are found at the address provided by the effective address computation. |
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| mm/m64 | An MMX register or a 64-bit memory operand. The 64-bitMMX registers are: MM0 through MM7. The contents of memory are found at the address provided by the effective address computation. |
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The byte count includes the opcode length and length of any required displacement or immediate data. If the displacement is optional, it is shown as d() with the possible lengths in parentheses. If the immediate data is optional, it is shown as i() with the possible lengths in parentheses.
