Intel Pentium CPU Instruction Set Reference

Basic Architecture Overview

General purpose registers

EAX	Accumulator. Accumulator for operands and results data.
EBX	Base. Pointer to data in the DS segment.
ECX	Count. Counter for string and loop operations.
EDX	Data. I/O pointer.
ESI	Source Index. Pointer to data in the segment pointed to by the DS register; source pointer for string operations.
EDI	Destination Index. Pointer to data (or destination) in the segment pointed to by the ES register; destination pointer for string operations.
EBP	Base Pointer. Pointer to data on the stack (in the SS segment).

EAX (32-bit)   AX (16-bit) AH (8-bit) AL (8-bit) EBX (32-bit)   BX (16-bit) BH (8-bit) BL (8-bit) ECX (32-bit)   CX (16-bit) CH (8-bit) CL (8-bit) EDX (32-bit)   DX (16-bit) DH (8-bit) DL (8-bit)

EBP (32-bit)   BP (16-bit) ESI (32-bit)   SI (16-bit) EDI (32-bit)   DI (16-bit) ESP (32-bit)   SP (16-bit)

Segment registers

CS	Code Segment.
DS	Data Segment.
SS	Stack Segment.
ES	Extra Data Segment.
FS	Extra Data Segment.
GS	Extra Data Segment.

Special purpose registers

EIP	Instruction Pointer. Pointer to the next instruction in a code segment. Automatically updated.
ESP	Stack pointer. Pointer to the top of the stack (in the SS segment). Used with POP, PUSH, CALL, etc.

EIP (32-bit)   IP (16-bit)

ESP (32-bit)   SP (16-bit)

EFLAGS register

EFLAGS	Flags. The state of various conditions in the cpu. The purpose of individual bits of the EFLAGS register is described below.

15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
	Nested Task	I/O privilege level		Overflow	Direction	Interrupt	Trap	Sign	Zero		Auxiliary Carry		Parity		Carry

• Carry (CF): Holds the carry out after addition or the borrow after subtraction. Also indicates error conditions.
• Parity (PF): 0 for odd number of bits and 1 for even. Obsolete feature of the 80x86.
• Auxiliary Carry (AF): Highly specialized flag used by DAA and DAS instructions after BCD addition or subtraction.
• Zero (ZF): 1 if the result of an arithmetic or logic instruction is 0.
• Sign (SF): 1 if the sign of the result of an arithmetic or logic instruction is negative.
• Trap (TF): Trap enable. The microprocessor interrupts the flow of instructions on conditions indicated by the debug and control registers.
• Interrupt (IF): Controls the operation of the INTR (Interrupt request) pin. If 1, interrupts are enabled. Set by STI and CLI instructions.
• Direction (DF): Specifies increment or decrement mode for the DI and/or SI registers during string instructions. If 1, registers are automatically decremented. Set by STD and CLD instructions.
• Overflow (OF): Set for addition and subtraction instructions.
• I/O privilege level (IOPL): Holds the privilege level at which your code must be running in order to execute any I/O-related instructions. 00 is the highest.
• Nested Task (NT): Set when one system task has invoked another through a CALL instruction in protected mode.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										Identification	Virtual Interrupt Pending	Virtual Interrupt Flag	Alignment Check	Virtual Mode	Resume

• Resume (RF): Used with debugging to selectively mask some exceptions.
• Virtual Mode (VM): When 0, the CPU can operate in Protected mode, 286 Emulation mode or Real mode. When set, the CPU is converted to a high speed 8086. This bit has enormous impact.
• Alignment Check (AC): Specialized instruction for the 80486SX.
• Virtual Interrupt Flag (VIF): Copy of the interrupt flag bit.
• Virtual Interrupt Pending (VIP): Provides information about a virtual mode interrupt.
• Identification (ID): Supports the CPUID instruction, which provides version number and manufacturer information about the microprocessor.

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