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Intel Pentium CPU Instruction Set Reference

CMPXCHG8B instruction - Compare and Exchange 8 Bytes

Code Mnemonic Description
0F C7 /1 m64 CMPXCHG8B m64 Compare EDX:EAX with m64. If equal, set ZF and load ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX.


Compares the 64-bit value in EDX:EAX with the operand (destination operand). If the values are equal, the 64-bit value in ECX:EBX is stored in the destination operand. Otherwise, the value in the destination operand is loaded into EDX:EAX. The destination operand is an 8-byte memory location. For the EDX:EAX and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the low-order 32 bits of a 64-bit value.

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is written into the destination. (The processor never produces a locked read without also producing a locked write.)

Operands Bytes Clocks
mem, reg 3 + d(0 - 2) 10 NP


ID unaffected DF unaffected
VIP unaffected IF unaffected
VIF unaffected TF unaffected
AC unaffected SF unaffected
VM unaffected ZF sets if the destination operand and EDX:EAX are equal; otherwise it is cleared
RF unaffected AF unaffected
NT unaffected PF unaffected
IOPL unaffected CF unaffected
OF unaffected