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Intel Pentium CPU Instruction Set Reference

SGDT instruction - Store Global Descriptor Table Register

Code Mnemonic Description
0F 01 /0 SGDT m Store GDTR to m
0F 01 /1 SIDT m Store IDTR to m


Stores the contents of the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR) in the destination operand. The destination operand specifies a 6-byte memory location. If the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the lower 2 bytes of the memory location and the 32-bit base address is stored in the upper 4 bytes. If the operand-size attribute is 16 bits, the limit is stored in the lower 2 bytes and the 24-bit base address is stored in the third, fourth, and fifth byte, with the sixth byte filled with 0s.

The SGDT and SIDT instructions are only useful in operating-system software; however, they can be used in application programs without causing an exception to be generated.

See "LGDT/LIDT — Load Global/Interrupt Descriptor Table Register" in this chapter for information on loading the GDTR and IDTR.

Operands Bytes Clocks
mem48 5 4 NP


ID unaffected DF unaffected
VIP unaffected IF unaffected
VIF unaffected TF unaffected
AC unaffected SF unaffected
VM unaffected ZF unaffected
RF unaffected AF unaffected
NT unaffected PF unaffected
IOPL unaffected CF unaffected
OF unaffected