| Code | Mnemonic | Description |
|---|---|---|
| 88 / r | MOV r/m8, r8 | Move r8 to r/m8 |
| 89 / r | MOV r/m16, r16 | Move r16 to r/m16 |
| 89 / r | MOV r/m32, r32 | Move r32 to r/m32 |
| 8A / r | MOV r8, r/m8 | Move r/m8 to r8 |
| 8B / r | MOV r16, r/m16 | Move r/m16 to r16 |
| 8B / r | MOV r32, r/m32 | Move r/m32 to r32 |
| 8C / r | MOV r/m16, Sreg | Move segment register to r/m16 (In 32-bit mode, the assembler may insert the 16-bit operand-size prefix with this instruction) |
| 8E / r | MOV Sreg, r/m16 | Move r/m16 to segment register (In 32-bit mode, the assembler may insert the 16-bit operand-size prefix with this instruction) |
| A0 | MOV AL, moffs8 | Move byte at (seg:offset) to AL (The moffs8, moffs16, and moffs32 operands specify a simple offset relative to the segment base, where 8, 16, and 32 refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16 or 32 bits.) |
| A1 | MOV AX, moffs16 | Move word at (seg:offset) to AX The moffs8, moffs16, and moffs32 operands specify a simple offset relative to the segment base, where 8, 16, and 32 refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16 or 32 bits.) |
| A1 | MOV EAX, moffs32 | Move doubleword at (seg:offset) to EAX The moffs8, moffs16, and moffs32 operands specify a simple offset relative to the segment base, where 8, 16, and 32 refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16 or 32 bits.) |
| A2 | MOV moffs8, AL | Move AL to (seg:offset) The moffs8, moffs16, and moffs32 operands specify a simple offset relative to the segment base, where 8, 16, and 32 refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16 or 32 bits.) |
| A3 | MOV moffs16, AX | Move AX to (seg:offset) The moffs8, moffs16, and moffs32 operands specify a simple offset relative to the segment base, where 8, 16, and 32 refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16 or 32 bits.) |
| A3 | MOV moffs32, EAX | Move EAX to (seg:offset) The moffs8, moffs16, and moffs32 operands specify a simple offset relative to the segment base, where 8, 16, and 32 refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16 or 32 bits.) |
| B0 + rb | MOV r8, imm8 | Move imm8 to r8 |
| B8 + rw | MOV r16, imm16 | Move imm16 to r16 |
| B8 + rd | MOV r32, imm32 | Move imm32 to r32 |
| C6 / 0 | MOV r/m8, imm8 | Move imm8 to r/m8 |
| C7 / 0 | MOV r/m16, imm16 | Move imm16 to r/m16 |
| C7 / 0 | MOV r/m32, imm32 | Move imm32 to r/m32 |
Copies the second operand (source operand) to the first operand (destination operand). The source operand can be an immediate value, general-purpose register, segment register, or memory location; the destination register can be a general-purpose register, segment register, or memory location. Both operands must be the same size, which can be a byte, a word, or a doubleword.
The MOV instruction cannot be used to load the CS register. Attempting to do so results in an invalid opcode exception (#UD). To load the CS register, use the far JMP, CALL, or RET instruction.
If the destination operand is a segment register (DS, ES, FS, GS, or SS), the source operand must be a valid segment selector. In protected mode, moving a segment selector into a segment register automatically causes the segment descriptor information associated with that segment selector to be loaded into the hidden (shadow) part of the segment register. While loading this information, the segment selector and segment descriptor information is validated (see the "Operation" algorithm below). The segment descriptor data is obtained from the GDT or LDT entry for the specified segment selector.
A null segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers without causing a protection exception. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded with a null value causes a general protection exception (#GP) and no memory reference occurs.
Loading the SS register with a MOV instruction inhibits all interrupts until after the execution of the next instruction. This operation allows a stack pointer to be loaded into the ESP register with the next instruction (MOV ESP, stack-pointer value) before an interrupt occurs 1. The LSS instruction offers a more efficient method of loading the SS and ESP registers.
When operating in 32-bit mode and moving data between a segment register and a general-purpose register, the Intel Architecture 32-bit processors do not require the use of the 16-bit operand-size prefix (a byte with the value 66H) with this instruction, but most assemblers will insert it if the standard form of the instruction is used (for example, MOV DS, AX). The processor will execute this instruction correctly, but it will usually require an extra clock. With most assemblers, using the instruction form MOV DS, EAX will avoid this unneeded 66H prefix. When the processor executes the instruction with a 32-bit general-purpose register, it assumes that the 16 least-significant bits of the general-purpose register are the destination or source operand. If the register is a destination operand, the resulting value in the two high-order bytes of the register is implementation dependent. For the Pentium Pro processor, the two high-order bytes are filled with zeros; for earlier 32-bit Intel Architecture processors, the two high order bytes are undefined.
| Operands | Bytes | Clocks | |
|---|---|---|---|
| reg, reg | 2 | 1 | UV |
| mem, reg | 2 + d(0 - 2) | 1 | UV |
| reg, mem | 2 + d(0 - 2) | 1 | UV |
| mem, imm | 2 + d(0 - 2) + i(1, 2) | 1 | UV ( not pairable if there is a displacement and immediate) |
| reg, imm | 2 + i(1, 2) | 1 | UV |
| acc, mem | 3 | 1 | UV |
| mem, acc | 3 | 1 | UV |
| Operands | Bytes | Clocks | |
|---|---|---|---|
| seg, r16 | 2 | 2 - 11 | NP |
| seg, m16 | 2 + d(0, 2) | 3 - 12 | NP |
| r16, seg | 2 | 1 | NP |
| m16, seg | 2 + d(0, 2) | 1 | NP |
| Operands | Bytes | Clocks | |
|---|---|---|---|
| seg, r16 | 2 | 2 - 11 (add 8 if new descriptor; add 6 if SS) | NP |
| seg, m16 | 2 + d(0, 2) | 3 - 12 (add 8 if new descriptor; add 6 if SS) | NP |
| Operands | Bytes | Clocks | |
|---|---|---|---|
| r32, cr32 | 3 | 4 | NP |
| cr32, r32 | 3 | 12/22 (cycles depend on which special register) | NP |
| r32, dr32 | 3 | 2/12 (cycles depend on which special register) | NP |
| dr32, r32 | 3 | 11/12 (cycles depend on which special register) | NP |
| r32, tr32 | 3 | - | NP |
| tr32, r32 | 3 | - | NP |
| ID | unaffected | DF | unaffected |
|---|---|---|---|
| VIP | unaffected | IF | unaffected |
| VIF | unaffected | TF | unaffected |
| AC | unaffected | SF | unaffected |
| VM | unaffected | ZF | unaffected |
| RF | unaffected | AF | unaffected |
| NT | unaffected | PF | unaffected |
| IOPL | unaffected | CF | unaffected |
| OF | unaffected |
